一种典型循环码的FPGA实现  

FPGA Realization of One Typicle Linear Block Code

作　　者：吴晟祖[1] 仲顺安[1] 陈越洋[1] 党华[1] 

机构地区：[1]北京理工大学,北京100081

出　　处：《机械与电子》2005年第8期20-22,共3页Machinery & Electronics

摘　　要：根据循环码的编码译码基本原理,给出了一种简明的循环码设计方法,利用这种方法,可以方便地在通信系统中实现低位数信道的编码译码,具有较高的编码效率。针对实际应用系统,设计并实现了一种基于典型的(15.7)循环码的信道编码,并且应用于基于FPGA开发的数据通信系统中。Based on the coding and decoding theory of cyclic code, a concise constructing method is presented in this paper. Low number channel coding and decoding can be easily applied in communication system by this method with high coding effi cod ciency. Here we e based on typical have schemed out a channel （15,7）cyclic code, and presented two matched programs aimed at practical application system.

关 键 词：线形分组码 循环码 FPGA 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]