换流阀合成试验回路建模及仿真  

Simulation of a Synthetic Test Circuit for HVDC Thyristor

作　　者：张家奇[1] 于飞[2] 刘喜梅[1] 

机构地区：[1]青岛科技大学自动化与电子工程学院,青岛266042 [2]北京理工大学二系,北京100081

出　　处：《高电压技术》2005年第8期51-53,共3页High Voltage Engineering

摘　　要：为研究现代电力系统高功率等级晶闸管换流阀的性能测试问题,提出了一个换流阀合成试验回路模型,采用独立的电压源和电流源,通过电压引入电流源的方法完成了几个试验项目,在EMTDC/PSCAD下得到的仿真结果与理想结果一致,证明该合成试验回路能测试换流阀。Due to a high power rate and difficulty in being tested in a common condition of mordern power thyristor valves the synthetic test circuit is put forward. The key to design a synthetic test circuits is to correctly reproduce the stresses applied on the thyristor valves. This paper proposes a model of synthetic test circuits, it adopts the independent voltage source and electric current source, and it introduces the method of the electric current source through the voltage. Then, this paper implements several experimental projects and obtains the artificial result. The result is identical with the ideal result. So it verifies that the synthetic test circuit is correct in theory.

关 键 词：合成试验回路 EMTDC/PSCAD 模型 

分 类 号：TM743[电气工程—电力系统及自动化]