应用于AVS视频解码器的VLD设计  

Design of Variable Length Decoder for AVS

作　　者：赵阳生[1] 黄晁[2] 刘明业[1] 

机构地区：[1]北京理工大学ASIC研究所,北京100081 [2]中国科学院计算技术研究所,北京100080

出　　处：《微机发展》2005年第9期122-124,共3页Microcomputer Development

摘　　要：设计了一种可应用于国家标准AVS(Audio Video Coding Standard)的变字长解码器,根据码流特点进行硬件模块划分;采用桶形移位器并行解码,每个时钟解一个码字,采用Verilog语言进行设计、模拟,通过了FPGA验证。用0.18μmCMOS工艺库综合,电路规模为1.6万门左右,最高频率能够达到166MHz,可实时解码720p/1080i高清AVS码流。Proposed an implementation of variable length decoder for national standard AVS. The design is separated into several parts according to the specialty of the code flow. The Barrel-Shifters which are based on parallel structure can decode one code per cycle. The module is designed, simulated based on Verilog HDL. The whole design has been verified by FPGA. The design consists of 16k gates when synthesized based on 0.18μm CMOS library. The highest frequency can reach 166MHz. The realized system can decode the 720p/1080i HD（High-Definition） AVS video in real-time.

关 键 词：视频解码 变字长解码 AVS 

分 类 号：TN919.81[电子电信—通信与信息系统]