基于SRAM高速灵敏放大器的分析与设计  

Analysis and Design of High Speed Sensible Amplifier for SRAM

作　　者：姚建楠[1] 季科夫[1] 吴金[1] 黄晶生[1] 刘凡[1] 

机构地区：[1]东南大学无锡分校,南京210096

出　　处：《电子器件》2005年第3期651-654,共4页Chinese Journal of Electron Devices

摘　　要：在SOC系统级芯片中,存储器占有很重要的地位。随着电路频率的提高,存储器的读写操作速度也要求相应的加快。SRAM中的灵敏放大器通过检测位线上的微小变化并放大到较大的信号摆幅以减少延时,降低功耗。本文提出了一种两级串联结构的SRAM高性能灵敏放大器的设计方法,降低了对信号的反应时间,提高了抗干扰能力,适应高频电路的读写操作。With steep increase of the frequency circuit, the speed of memory read/write operation in SOC system needs to improve correspondingly. The amplifier reduces delay time and power dissipation by detecting small transitions on the bit line and amplifying them to large signal swings. This paper proposes a method for the design of sensible high performance amplifier, which improves the noise immunity and response time, adapting to the high frequency read/write operation in SRAM.

关 键 词：SOC 存储器 SRAM 灵敏放大器 

分 类 号：TN492[电子电信—微电子学与固体电子学]