基于FPGA芯片的数字频率计设计  

Digital Cymometer Design Based on FPGA

作　　者：谢海鸿[1] 李萍[1] 林德彬[1] 

机构地区：[1]佛山科学技术学院电子信息工程系,广东佛山528000

出　　处：《现代电子技术》2005年第18期13-14,16,共3页Modern Electronics Technique

摘　　要：介绍了一种利用EDA技术设计的数字频率计。目前流行的EDA软件平台是美国Altera公司的Max+Plus可编程逻辑器件开发系统。本文采用自顶向下的设计方法,对数字频率计的核心——十进制计数器和测频控制信号发生器进行设计,其特点是将数字频率计的电路集成在一块大规模可编程逻辑器件(FPGA)芯片上。该方法改变了以往数字电路小规模多器件组合的设计,而且设计周期短,内部电路模块具有可移植等特点。与用其他方法做成的频率计相比,其体积更小、性能更可靠。This paper discusses the digital cymometer design principles by using EDA technology. It is used in the paper that a kind of popular EDA software -Max＋Plus Ⅱ programmable logic device development system developed by American Altera Company. The writer has adopted the design idea of top graphic to design the core chip, a decimal counter and a frequency controlling signal generator. Particularly, the circuit of the digital cymometer is designed on a grand scale programmable logic device FPGA. This software procedure is different from the traditional digital circuit design composed of many small scale devices. Furthermore, the circuit design cycle is short,and parts of the circuit are transplantable. Comparing with other cymometer,it is smaller in volume and more reliable in functions.

关 键 词：数字频率计 FPGA EDA VHDL 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构]