采用交流能源的低功耗CPL电路  

Low Power CPL Circuits Employing AC Power Supply

作　　者：胡建平[1] 叶锡恩[1] 汪鹏君[1] 

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《固体电子学研究与进展》2005年第3期391-397,共7页Research & Progress of SSE

基　　金：浙江省自然科学基金资助项目(No.Y104327);浙江省教育厅科研项目(No.20030487)资助

摘　　要：从改变CMOS电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性.在此基础上提出了一种仅由nMOS构成的低功耗绝热电路--nMOS Complementary Pass-transistor Adiabatic Logic(nCPAL).该电路利用nMOS管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积.nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低.采用TSMC的0.25 μm CMOS工艺,设计了一个8-bit超前进位加法器和功率时钟产生器.版图后仿真表明,在50～200 MHz频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N2P电路的50%和35%.研究表明nCAPL适合于在VLSI设计中对功率要求较高的应用场合.In view of changing the type of energy conversion in CMOS circuits, this paper investigates the low-power characteristic of complementary pass-transistor logic （CPL） circuits employing AC power clock. On this basis, a new nMOS complementary pass-transistor adiabatic logic （nCPAL） is presented, which uses nMOS transistors only. The bootstrapped nMOS switch is employed to eliminate non-adiabatic loss of output loads and to simplify nCPAL circuits. Its energy dissipation is less dependency on power-clock frequency and insensitivity to output load capacitance. An 8-bit carry-lookahead adder based on nCPAL and a power clock generator were designed and verified. In layout-based simulations with TSMC 0.25μm CMOS process, the 8-bit nCPAL adder consumed only 35% of the dissipated energy of a 2N-2N2P adder and is about 50% of the dissipated energy of a PAL-2N adder for clock rates ranging from 50 to 200 MHz. In conclusion, our investigation shows that nCPAL is an excellent candidate for low-energy VLSI design.

关 键 词：低功耗设计 钟控CPL电路 绝热逻辑 超前进位加法器 交流能源 CMOS电路 低功耗 CPL VLSI设计 CMOS工艺 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN791