20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS  

0.18μm CMOS 20Gb/s 1∶2分接器设计(英文)

作　　者：王贵[1] 王志功[1] 王欢[1] 丁敬峰[1] 熊明珍[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Semiconductors》2005年第10期1881-1885,共5页半导体学报（英文版）

基　　金：国家高技术研究发展计划资助项目(批准号:2001AA312050)~~

摘　　要：A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.使用标准0.18μm CMOS工艺设计并实现了1∶2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽, 在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.

关 键 词：DEMULTIPLEXER LATCH CMOS high-speed circuit 

分 类 号：TN432[电子电信—微电子学与固体电子学]