The National High Technology Research and Devel-opment Program of China (863Program) (No2001AA312010)
A design of a ll. 6-GHz phase-locked loop (PLL) fabricated in 49-GHz 0. 18-μm CMOS (complementary metal-oxide-semiconductor transistor) technology is described. An analog multiplier phase detector (PD), a one-p...
This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and...
The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, ...
The National High Technology Research and Devel-opment Program of China (863Program) (No.2001AA312010).
A 10 Gbit/s 1:4 demultiplexer(DEMUX) fabricated in 0. 18 μm CMOS (complementary metal-oxidesemiconductor transistor) technology for optical-fiber-link is presented. The system is constructed in tree-type structu...