A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer  

一种低功耗的10Gbit/s CMOS1∶4分接器(英文)

作　　者：蒋俊洁[1] 冯军[1] 李有慧[1] 胡庆生[1] 熊明珍[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Southeast University(English Edition)》2006年第1期1-4,共4页东南大学学报（英文版）

基　　金：The National High Technology Research and Devel-opment Program of China (863Program) (No.2001AA312010).

摘　　要：A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.采用TSMC0·18μm CMOS工艺实现了一种应用于光纤通信系统SDH STM-64的10Gbit/s1∶4分接器,整个系统采用树型结构,由1个高速1∶2分接器、2个低速1∶2分接器、分频器以及数据和时钟输入输出缓冲组成.为达到优化性能、降低功耗的目标,其中高速分接部分和5GHz1∶2分频器都采用共栅结构、单时钟输入的锁存器;而低速分接部分则由动态CMOS逻辑实现.通过在片晶圆测试,该芯片在输入10Gbit/s、长度为231-1的伪随机码流时工作性能良好,电源电压1·8V,功耗仅为100mW.芯片面积为0·65mm×0·75mm.

关 键 词：optical communication CMOS demultiplexer （DEMUX） LOW-POWER 

分 类 号：TN722[电子电信—电路与系统]