基于FPGA的CMOS图像敏感器驱动电路设计  

Design on Driving Circuit Based on FPGA Technology for CMOS Image Sensor

作　　者：白喆[1,2] 张伯珩[1] 边川平[1] 

机构地区：[1]中国科学院西安光学精密机械研究所 [2]中国科学院研究生院,北京100048

出　　处：《科学技术与工程》2005年第19期1317-1320,共4页Science Technology and Engineering

摘　　要：介绍了一种用于卫星姿态测量的CMOS图像敏感器——STAR250,分析了其驱动时序信号,选用现场可编程门阵列(FPGA)作为硬件设计平台,使用VHDL语言对驱动时序电路进行了硬件描述,经布线、仿真、测试后验证了驱动信号的正确性。The STAR250, a kind of CMOS Image Sensor, which is used to survey the satellite state was described. And the driving schedules signal of the STAR250 was analysed. FPGA was selected to be the hardware design flat roof. VHDL are used to describe the hardware of the driving schedules circuit. The experiment result indicates that the design is virtual.

关 键 词：FPGA STAR250 CMOS图像敏感器 VHDL 

分 类 号：TN919.85[电子电信—通信与信息系统]