异步组合电路网表优化的研究  

Research on Netlist Optimization of Asynchronous Combinational Logic Circuits

作　　者：单智阳[1] 王颀[1] 刘丽蓓[1] 邵丙铣[1] 

机构地区：[1]复旦大学国家微电子材料与元器件微分析中心,上海200433

出　　处：《微电子学与计算机》2005年第11期144-147,共4页Microelectronics & Computer

摘　　要：根据异步组合电路的特点,本章在传统的工艺映射算法的分解和覆盖两个步骤之间引进了新的一步—“延时再优化”,采用NAND3-Rotation的方法实现,对分解后网表的平均延时进行优化。在标准测试电路上的测试结果表明引进延时再优化能给异步电路的平均延时带来6～25%的改进。According to the character of asynchronous combinational logic circuits, this paper presents a new step, which is named “re-optimization for delay” here, between traditional decomposition and coverage in the process of technology mapping .This step is implemented with the algorithm of NAND3-Rotation and optimizes the average delay of the decomposed netlist. The experimental results on a set of benchmark circuits show that this algorithm can improve the average delay of asynchronous circuits by 6～25%.

关 键 词：异步电路 工艺映射 平均延时 延时再优化 

分 类 号：TN302[电子电信—物理电子学]