基于CPLD的CCD图像敏感器驱动时序设计  

Design on Driving Schedules Based on CPLD Technology for CCD Image Sensor

作　　者：白喆[1] 张伯珩[1] 边川平[1] 

机构地区：[1]中国科学院西安光学精密机械研究所

出　　处：《科学技术与工程》2005年第20期1491-1493,共3页Science Technology and Engineering

摘　　要：介绍了一种CCD图像敏感器——TCD142D,分析了其驱动时序信号,选用复杂可编程逻辑器件(CPLD)作为硬件设计平台,使用VHDL语言对驱动时序发生器进行了硬件描述,采用QuartusII对所设计的时序发生器进行了仿真,针对Altera公司的可编程逻辑器件EPM7064SLC44进行适配。实验结果表明,驱动时序发生器的设计是正确的,可以满足CCD工作驱动要求。The TCD142D was described. The driving schedules pulse of the TCD142D was analysed. CPLD was selected to be the hardware design flat roof. VHDL is used to describe the hardware of the driving schedules generator. Quartus Ⅱ is used to simulate the schedules. EPM7064SLC44 is adapted to the system. The experiment result indicates that the design of driving schedules generator is virtual. And it meet with the task of CCD.

关 键 词：CPLD TCD142D CCD图像敏感器 VHDL 

分 类 号：TN386[电子电信—物理电子学]