一种用于ADC电路的高速高精度比较器设计  

High-Speed High-Resolution Comparator for Design of ADC

作　　者：吴光林[1] 吴建辉[1] 杨军[1] 饶进[1] 罗春[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏南京210096

出　　处：《应用科学学报》2005年第6期591-594,共4页Journal of Applied Sciences

基　　金：国家自然科学基金资助项目(60176018)

摘　　要：在分析各种比较器设计失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器设计技术和失调消除技术.该比较器由主动复位和被动箝位的预放大器和输出锁存器构成,具有失调自动校准功能.仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3 V,调整后的比较器失调误差为56.8μV,比较器的精度0.1mV,比较速率100 MHz.In this paper, various offset-canceling techniques in comparators are reviewed, and high-speed high-resolution comparator design techniques and a new offset canceling technique are then described. The comparator includes three preamplifiers, an output latch and offset canceling circuit. Experimental results show that, after offset adjusting of the comparator, an offset error of about 56.8μV is achieved, and it is able to resolve 0.1 mv at a comparison rate of 100 MHz under the condition of a single ＋ 3.3 supply using Chartered 0.35μm CMOS technology.

关 键 词：A/D转换器 比较器 失调消除技术 放大器 

分 类 号：TN432[电子电信—微电子学与固体电子学]