THE DESIGN OF VMEBUS BRIDGE CONTROLLER WITH SHARC BUS  

作　　者：Wang Min Wu Shunjun Su Tao 

机构地区：[1]Key Lab for Radar Signal Processing, Xidian University, Xi＇an 710071, China

出　　处：《Journal of Electronics(China)》2005年第6期632-639,共8页电子科学学刊（英文版）

摘　　要：Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit （IC）, this paper presents a scheme of adopting CPLD/FPGA （Complicated Programmable Logic Device/Field Programmable Gate Array） to design bridge controller between VMEbus and local bus. SHARC DSP （Digital Signal Processor） bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA （Direct Memory Access） controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.

关 键 词：VMEBUS Bridge controller Complicated Programmable Logic Device（CPLD） Master SLAVE SHARC bus 

分 类 号：TN911.72[电子电信—通信与信息系统]