USB中的CRC校验原理及其Verilog HDL语言实现  

CRC principle in USB and implementing with Verilog HDL

作　　者：廖坚[1] 于海勋[1] 

机构地区：[1]西北工业大学,陕西西安710072

出　　处：《计算机工程与设计》2005年第11期3127-3129,共3页Computer Engineering and Design

摘　　要：在数据和控制信息中加上循环冗余码是通用串行总线(USB)协议中一个重要的错误检测措施。接收端通过进行循环冗余校验(CRC),可以检测包在传输过程中是否发生损坏。硬件描述语言VerilogHDL常用于数字电子系统性设计,设计者可用它进行各种级别的逻辑设计。介绍了循环冗余码基本原理、USB协议中的循环冗余校验以及CRC校验的串、并行设计和Verilog HDL代码实现。As an important error detection measure, CRC protects over control and data fields in USB Specification. By the CRC Computation, receiver can detect whether packet has been corrupted during transport. The Verilog Hardware Description Language is often used to design digital electronic systems, and designer can use it to describe the logic of electronic systems at different levels of abstraction. The basal principle of cyclic redundancy code and cyclic redundancy check in USB specification were introduced. The circuits and Verilog HDL programs which design for serial or parallel CRC computation were also introduced.

关 键 词：通用串行总线 循环冗余校验 VERILOG HDL代码 仿真 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]