基于VerilogHDL的IP核参数化设计  

Parameterized IP Core Design Based on VerilogHDL

作　　者：徐晨[1] 袁红林[1] 

机构地区：[1]南通大学江苏省专用集成电路设计重点实验室,江苏南通226007

出　　处：《微电子学与计算机》2005年第12期85-88,共4页Microelectronics & Computer

基　　金：上海市科委SDC专项计划资助(037062026)

摘　　要：指出了IP核参数化设计的重要性,分析了IP核的参数类型及相互关系。在分析基于VerilogHDL的IP核参数化设计方法及所面临困难的基础上,提出了一种附加的编译预处理方法并设计了相应的工具软件ECP。IP核由VerilogHDL和ECP扩展的语句混合编程,经ECP处理后生成VerilogHDL源文件。应用该方法后,提高了Ver-ilogHDL在描述功能、性能、结构及优化策略等参数化的复杂模型时所需要的灵活性,增强了VerilogHDL的建模能力。作为一个IP核参数化设计的实例,介绍了C*Core系统中断控制IP的参数化设计过程,给出了FPGA验证的结果。The importance of IP parameterized design is pointed out and the parameter type and correlation are analyzed in this paper. After analyzing parameterized IP design methodology based on VerilogHDL and its difficulties, a kind of additive compile-preprocess methodology and its software tool namely ECP are proposed. IP core is described in VerilogHDL and ECP extended sentence that is then processed by ECP and the goal VerilogHDL file is created. So the hardware description flexibility is enhanced when design complicated model with function, performance, structure and optimization related parameters. As a parameterized IP core example, C＊Core interrupt controller IP is introduced to present the parameterized design procedure and the experimental result is presented.

关 键 词：IP核 参数化设计 VERILOGHDL 编译预处理 中断控制IP 

分 类 号：TN402[电子电信—微电子学与固体电子学]