基于∑△ 调制的分数频率综合器杂散分析  

The Analysis of Spur Suppression of Fractional-N Frequency Synthesizers Based on ∑-△ Modulation Technology

作　　者：伍岳[1] 张玉兴[1] 

机构地区：[1]电子科技大学电子工程学院,成都610054

出　　处：《电子对抗》2005年第6期18-21,共4页Electronic Warfare

摘　　要：分数频率综合器能在提供小步进跳频距离的同时达到比较好的相噪指标，故得到了广泛的应用。但是，由于分数频率综合器会在跳频步进处出现特有的分数杂散，故其性能受到了分数杂散的影响而恶化。因此，减小分数杂散的影响成为了分数频率综合器应用中的重要内容。∑-△调制技术来源于高速的A／D、D／A转换技术，该技术已广泛应用于现代PLL芯片中，文章详细介绍了∑-△调制技术，并对其抑制分数频率综合器杂散的性能进行了深入分析。The fractional-N frequency synthesizers are widely used because of the good phase-noise performance while giving small frequency steps. But, the fractional spur will appear at the channel spacing in fractional PLL, the performance worsens for its own spur influence. So, it is important to reduce this kind of influence. In this paper, we discuss the ∑-△ modulation technology coming from high-speed A/D and D/A technology which is widely used in the PLL chips, and analyze its characteristic for spur suppression of fractional-N frequency synthesizers.

关 键 词：∑-△调制 杂散量化噪声 过采样 分数频率综合器 

分 类 号：TN74[电子电信—电路与系统] TN742.1