多时钟域处理器架构的性能和功耗分析  

Performance and Power Analysis of Multiple Clock Domain Processor Architecture

作　　者：朱晓冬[1] 王世明[1] 

机构地区：[1]上海交通大学电子工程系,上海200030

出　　处：《计算机工程》2005年第24期75-77,共3页Computer Engineering

基　　金：国家"863"计划基金资助项目(2002AA1Z1120)

摘　　要：研究一种新的多时钟域的处理器架构,它把处理器分成几个工作在不同时钟下的时钟域,每个域有自己独立的工作电压和时钟频率,可以大大缓解高速处理器设计中最棘手的全局时钟分布问题,并且每个域的工作电压和工作频率可以根据应用的实际需求动态地调整,可以平均节省约20%的功耗。此外分析了全局异步局部同步时钟方案的结构及电压和工作频率调整的算法,并给出用SimpleScalar和Wattch仿真工具得到的仿真结果。This paper describes an alternative approach, which is called a multiple clock domain processor, in which the chip is divided into several clock domains, within which independent voltage and frequency scaling can be performed. Since the clock frequency and voltage of each domain can be scaled as the demand of practical applications, about 20% power dissipation can be saved averagely. In additionit the paper analyzes the architecture of globally asynchronous locally synchronous processor and the algorithms of dynamically reconfiguring the clock frequency and voltage.

关 键 词：处理器 多时钟域 低功耗 

分 类 号：TN402[电子电信—微电子学与固体电子学]