基于VHDL的滴灌控制系统及定时器的设计  

The Dsign of Control System and Timer in Drop-irrigating System Based in VHDL

作　　者：冯燕尔[1] 赵燕伟[2] 林学龙[3] 

机构地区：[1]浙江海洋学院,浙江舟山316000 [2]浙江工业大学,浙江杭州310032 [3]上海大学,上海200436

出　　处：《机电工程》2005年第12期22-25,共4页Journal of Mechanical & Electrical Engineering

摘　　要：滴灌控制系统的定时器是滴灌系统控制模块的一个重要器件。介绍了一种滴灌控制器的系统工作原理、计算机控制系统的组成和定时器芯片CPLD/FPGA的逻辑功能,设计了滴灌控制系统的核心元件定时器;重点讲述了采用VHDL进行滴灌控制定时器ASIC的设计思路,并对滴灌控制系统定时器的逻辑功能进行仿真。仿真结果表明,定时器能完成设计的复位、测试、定时和计时功能。The counter is an important instrument of the control model of the drop-irrigating system. This article introduces the principle of the drop - irrigating controller system, the hardware of the controller and the logical function of the counter chip CPLD/FPGA. It also introduces the design of the counter, the kernel component of the control model. It emphasis the train of thought of designing the counter ASIC by using VHDL language. It also showed by computer simulation that the counter can carry out those functions designed such as reset, test, counter, and so on.

关 键 词：滴灌控制器 定时器 VHDL 逻辑功能仿真 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置] S277.99[自动化与计算机技术—控制科学与工程]