10Gb/sCMOS时钟和数据恢复电路的设计  

A 10 Gb/s CMOS Clock and Data Recovery Circuit

作　　者：陈莹梅[1] 王志功[1] 赵海兵[1] 章丽[1] 熊明珍[1] 

机构地区：[1]东南大学射频和光电集成电路研究所,南京210096

出　　处：《固体电子学研究与进展》2005年第4期494-498,共5页Research & Progress of SSE

基　　金：国家863计划项目(No.2002AA312230)资助课题

摘　　要：介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。This paper introduces the design of a 10 Gb/s clock and data recovery circuit to be fabricated in 0. 18 μm CMOS technology. The circuit is to be used in the SDH STM-64 optical communication system. This paper adopts the Charge Pump PLL can detect the phase generating early-late phase logiPhase-Locked Loops （CPPLL） scheme. The phase detector in CPc and its special function is to sample the data to act as a 1 ; 2 demultiplexer. Employing a full integrated LC oscillator and a half rate PD, the recovered 5 GHz clock has a phase noise of --112 dBc/Hz at 1 MHz offset in response to 10-Gb/s PRBS input data（2^3l- 1）. The 10-Gb/s PRBS data have been demultiplexed to two 5-Gb/s data. The 1.00mm × 0. 8 mm IC consumes 158 mW under a single 1.8 V power supply.

关 键 词：时钟和数据恢复 LC压控振荡器 电荷泵锁相环 

分 类 号：TN929[电子电信—通信与信息系统]