OFDM系统中Viterbi译码器的设计及FPGA验证  

Design and FPGA Verification of a Viterbi Decoder in OFDM System

作　　者：郑宇驰[1] 周晓方[1] 闵昊[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2005年第6期923-928,934,共7页Journal of Fudan University：Natural Science

基　　金：国家"八六三"计划资助项目(2003AA1Z1120);上海市科委SDC资助项目(037062020)

摘　　要：在对Viterbi译码算法进行Matlab软件仿真的基础上,综合考虑硬件开销以及电力线OFDM传输系统中FEC解码的具体要求,确定了Viterbi译码器的各个设计参数.为了提高译码性能和译码速度,提出了一种改进的回溯算法.整个设计用Verilog语言编写,采用FPGA技术,通过系统联调,验证了设计的合理性与可靠性.Based on the simulation model of Viterbi algorithm with Matlab, taking hardware cost and forward error correction in powerline OFDM system into account, some key parameters of Viterhi decoder are determined. In order to enhance the performance and speed of Viterbi decoder, an improved trace-back scheme is proposed. The decoder is designed in Verilog language and with FPGA technology. The rationality and reliability of the decoder are verified.

关 键 词：半导体技术 VITERBI译码器 正交频分复用 现场可编程门阵列 回溯 

分 类 号：TN492[电子电信—微电子学与固体电子学]