一种改进的流水线模数转换器结构  

An Improved Pipelined ADC Architecture

作　　者：施宇峰[1] 许俊[1] 任俊彦[1] 陈诚[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2005年第6期977-982,共6页Journal of Fudan University：Natural Science

摘　　要：在分析传统每级1.5位流水线模数转换器的基础上,提出了一种改进结构,该结构完全解决了传统结构因为最后一级的量化电平失调造成的非单调性问题,仿真结果表明改进后的10比特模数转换器在实际情况下的有效位数(ENOB)最大约有0.83 bit的提高,且电路的功耗和面积增加量相对较小.Based on analysis of the traditional 1.5-bit/stage pipelined ADC an improved architecture is presented. The non-monotonlcity of the traditional architecture caused at the last stage is eliminated. Simulation results show that for the improved 10-blt pipelined ADC maximum 0.83-bit ENOB over the traditional one can be achieved without much increase in power dissipation and area as it is implemented.

关 键 词：数模混合集成电路 流水线模数转换器 单调性 量化失调 数字校正 

分 类 号：TN403[电子电信—微电子学与固体电子学]