基于VERILOG的一种高效验证平台的研究及应用  

Research and Application of an Efficient Testbench Based on Verilog

作　　者：董玲 张松 于宗光[1] 陶建中[1] 

机构地区：[1]江南大学,江苏无锡214122

出　　处：《微电子学与计算机》2006年第1期55-58,63,共5页Microelectronics & Computer

基　　金：国防科技重点实验室基金资助项目(51433020105DZ6801)

摘　　要：文章讨论了基于VERILOG验证平台的功能、组成、关键设计技术及优化几个方面的问题,并在此基础上用VERILOGHDL建立了高效的自检查验证平台,实现了被测模型的输出与期望输出的自动比较。Functions, constructs, critical design techniques and optimizations of the Verilog-based testbench were introduced in this paper. Based on these, an efficient self-check testbench written by Verilog HDL, which could compare the outputs of the DUT with the expected values automatically, was built.

关 键 词：验证平台 白检查 VERILOG HDL 结构优化 

分 类 号：TN407[电子电信—微电子学与固体电子学]