一种高阶除法器的设计与实现  

Design and Implementation of A Very-High Radix Floating-Point Division Unit

作　　者：白永强[1] 沈绪榜[1] 罗旻[1] 靳战鹏[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《微电子学与计算机》2006年第1期64-66,70,共4页Microelectronics & Computer

基　　金：国防"十五"预研课题(41308010108);西北工业大学研究生创业种子基金资助(Z20040050)

摘　　要：文章利用业界通用的FPSPEC92、FPSPEC95、LINPACK、WHETSTONE、FLOPS等浮点基准测试程序,基于阻塞步长对浮点处理性能进行分析。通过大量实验,得出浮点除法最佳执行周期为8～12拍。据此,为“龙腾R1”处理器设计了执行周期为11拍的基-256浮点除法器,并在SMIC0.18ΜM工艺下实现,恶劣环境下其运行速度为233MHZ,面积约为0.174MM2。By utilizing industrial floating-point benchmarks, such as fpspec92, fpspec95, linpack, whetstone and flops, based on the concept of interlock distance, floating-point processing performance is analyzed. From the experimental resuits, it can be concluded that the performance will be better when the cycle delay of floating-point division is between 8 and 12 cycles. So, the cycle delay of the division unit implemented as a radix-256 divider in ＂LongTeng＂ microprocessor is designated to be 11 cycles. It is implemented in SMIC 0.181μm 1P5M CMOS technology. In the worst environment, it＇s speed reaches 233MHZ, as well as the area is 0.174 mm^2.

关 键 词：浮点基准测试程序 阻塞步长 性能分析 高阶 浮点除法器 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]