深亚微米SOC芯片物理设计中基于串扰的时序收敛方法  

A Method of Timing Closure Based on Crosstalk in Deep-Submicrometer Physical Design of SoC Chip

作　　者：王丽英[1] 杨军[1] 罗岚[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏南京210096

出　　处：《微电子学与计算机》2006年第1期85-88,共4页Microelectronics & Computer

摘　　要：当芯片设计进入深亚微米,串扰效应引起大量的设计违规,尤其是对时序收敛产生很大的影响。实际上串扰对电路时序性能的影响非常难估计,它不仅取决于电路互联拓扑,而且还取决于连线上信号的动态特征。文章从串扰延时的产生原因开始分析,并提出了在0.18ΜM及以下工艺条件下对串扰延时进行预防,分析和修复的时序收敛方法。When SoC design goes into Deep-Submicrometer era, crosstalk effects cause a lot of design violations, especially to timing closure. In fact, it is difiqcult to estimate the crosstalk effects to circuit pertbrmance since it not only depends on interconnect topology but also lies on the signal dynamic characteristic. This paper studies the cause of crosstalk and then presents a method of how to prevent, analyze and fiX the crosstalk for timing closure in Deep-Submicrometer physical design of SoC chip.

关 键 词：深亚微米 串扰 时序收敛 

分 类 号：TN43[电子电信—微电子学与固体电子学]