一种基于流水线的指令CACHE优化设计  

An Optimized Design of Instruction Cache based on Pipeline

作　　者：田芳芳[1] 樊晓桠[1] 靖朝鹏[1] 靳战鹏[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《微电子学与计算机》2006年第1期93-96,共4页Microelectronics & Computer

基　　金：国防"十五"预研基金资助(41308010108)

摘　　要：在现代微处理器的设计中,CACHE是整个微处理器性能的决定性因素。本文详细介绍了32位RISC微处理器“龙腾”R2中指令CACHE的体系结构,着重研究了其设计和实现问题。为了提高性能,采用了预取技术和流水线技术来优化设计,仿真结果表明得到了预期的效果。Abstract： In the design of modem microprocessor, Cache has the decisive effect on the performance of microprocessor. This Paper presents the architecture of Instruction Cache of a 32-hit RISC microprocessor chip named＂LongTeng＂R2, the design and the implementation techniques of it are studied in detail. Inorder to improve the performance , the technique of Pipeline and prefetch are introduced,and the result of simulation shows that the design is achieve our purpose.

关 键 词：指令CACHE 流水线 存储子系统 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]