适用于1000Base-T以太网的低抖动低功耗频率综合器  

A Low-Jitter and Low-Power Frequency Synthesizer Applied to 1000Base-T Ethernet

作　　者：陆平[1] 王彦[1] 郑增钰[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《Journal of Semiconductors》2006年第1期137-142,共6页半导体学报（英文版）

摘　　要：采用高速鉴频鉴相器(TSPC)、经典抗抖动的电荷泵、交叉耦合差分延迟单元以及电阻分压相位内插电路等结构设计了一个应用于1000Base-T以太网收发器的频率综合器电路,并能兼容10/100Mbps模式.该电路同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟(128相)的需要,大大节约了面积和功耗.在晶振的绝对抖动σ约为16ps情况下,输出25MHz测试时钟信号σ仅为11ps.表明该频率综合器有较强的抑制噪声能力,能很好满足发送和接收电路对于时钟性能的要求.芯片采用SMIC0.18μm的标准CMOS工艺,电源电压为1.8V,功耗小于4mW.This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump, and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/ 100Mbps modes. This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising （falling） edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs, thus greatly saving area and power. The data show that the σ of the voltage control oscillator jittercycle-cycle is only 11ps while that of the reference clock jittercycle-cycle is 16ps. This indicates that the frequency synthesizer works well for transmitters and receivers. The circuit is designed with SMIC 0.18μm standard CMOS technology, the power supply is 1.8V, and the power is lower than 4mW.

关 键 词：以太网 频率综合器 时钟抖动 

分 类 号：TN492[电子电信—微电子学与固体电子学]