一种基于Wallace树的分散式DCT/IDCT体系结构  

A New DCT/IDCT Architecture Based on Wallace Trees

作　　者：黎铁军[1] 王爱平[1] 李思昆[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2006年第1期68-72,共5页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(90207019);国家863高技术研究发展计划基金资助项目(2002AA1Z1480)

摘　　要：提出了一种新的基于Wallace树的分散式DCT/IDCT体系结构。它不依赖于ROM和乘法器,用面积开销低的加法器、移位器和4-2压缩器,实现了乘法密集的DCT/IDCT算法。该体系结构在SMIC 0.18μm工艺上进行了设计和综合,可以达到100Mpixels/s的吞吐率,只消耗了36 141个晶体管和1024bits转换存储器,时序—面积性能较已有的体系结构有了显著的改善。This paper proposes a Wallace-tree based new DCT/IDCT architecture, which does not depend on ROM and multipliers any more, but utilizes low cost adders, shifts and 4 - 2 compressors to implement the multiplication-dense DCT/IDCT algorithm. Designed and synthesized by SMIC 0.18μml technology, the arcltitecture could achieve 100Mpixels/sec throughout with cost of only 36 141 transistors and 1024 bits transform memory. As a result, a far better performance of time series and space is obtained than that of the existing architecture.

关 键 词：MPEG DCT IDCT WALLACE树 体系结构 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]