基于CPLD的8位总线接口设计  

Design of 8-bits Bus Interface Based on CPLD

作　　者：谢付正[1] 郭树旭[1] 

机构地区：[1]吉林大学电子科学与工程学院,吉林长春130012

出　　处：《现代电子技术》2006年第6期79-80,88,共3页Modern Electronics Technique

摘　　要：基于CPLD技术设计了双通道总线接口并给出该接口的通道模型和控制方法。本接口采用存储器访问模式,克服了某些CPU外围通信接口少的缺点,易于实现双CPU间的总线对接,且无需考虑复杂的总线仲裁机制。该接口适用于双主机间的数据传输,具有使用方便、速率匹配、实时响应等优点。同时采用VHDL硬件描述语言,使设计易于模块化,也为基于CPLD的总线转换及其他接口电路的设计提供了新的思路。Based on CPLD （Complex Programmable Logic Device） 8- bits bus interface, channel model and control method are carried out. This type of bus interface can be accessed by memory mode and be applied to the exchange of data between two hosts,whlch can overcome the lack of communication interface in some types of CPU. It possesses the features of convenience, speed match and realtime response. Moreover, the modularization and reuse are easily to realize for the induction of VHDL （Very High Speed Integrated Circuit Hardware Description Language）. It also brings a new ideal for the conversation from bus to other interface circuits.

关 键 词：CPLD VHDL 总线接口 总线仲裁 

分 类 号：TN92[电子电信—通信与信息系统]