基于FPGA/CPLD的通用异步通信接口UART的设计  

The Design of UART(Universal Asynchronous Receiver Transmitter) based on FPGA/CPLD

作　　者：姜宁[1] 范多旺[2] 

机构地区：[1]光电技术与智能控制教育部重点实验室 [2]兰州交通大学自动控制研究所,甘肃兰州730070

出　　处：《信息技术与信息化》2006年第1期86-88,共3页Information Technology and Informatization

摘　　要：UART(通用异步接收发送设备)是一种短距离串行传输接口。在数字通信和控制系统中得到广泛应用。FPGA/CPLD是大规模集成电路技术发展的产物,是一种半定制的集成电路。结合计算机软件技术(EDA技术)可以快速、方便地构建数字系统。本文介绍一种采用可编程逻辑器件FPGA/CPLD实现UART的方法,将UART的核心功能集成到FPGA/CPLD上,本设计包含UART的发送模块、接收模块和波特率发生器,所有功能的实现全部采用VHDL硬件描述语言来进行描述。设计、综合、仿真在QUARTUSII软件开发环境下实现。UART （Universal Asynchronous Receiver Transmitter）is a short-haul serial communication interface which is applied widely in digital communication and control system. The result of LSI（Large Scale Integration） is FPGA/CPLD, it is the attribute of semi-custom Integrate Circuit, combining EDA with FPGA/CPLD will construct the digital system quickly and expediently. This article introduces a method to design uart based on the programmable logic device FPGA/CPLD. The core function of UART is integrated in FPGA/CPLD. This design includes the Trammitter Logic, the Receiver Logic and the Baudrate Generator. All function are given by VHDL. The implementation of design, simulation,synthesis is the software of QUARTUSII.

关 键 词：UART VHDL FPGA/CPLD 仿真 

分 类 号：TN791[电子电信—电路与系统]