快速3D DWT核心算法的VLSI并行化设计  

Paralell VLSI Design for the Fast 3D Discrete Wavelet Transform Core Algorithm

作　　者：魏本杰[1] 刘明业[1] 周艺华[1] 成宝栋[1] 

机构地区：[1]北京理工大学计算机科学技术学院

出　　处：《北京理工大学学报》2006年第3期211-215,共5页Transactions of Beijing Institute of Technology

基　　金：国家部委预研项目(41308010408)

摘　　要：通过深入研究三维离散小波变换(3D DWT)核心算法,将其分解为3个一维的小波变换(1D DWT).在完成3D DWT软件实现的基础上,提出了一种并行化设计的VLSI结构,由3个片上双口RAM存储中间结果并进行矩阵转置,建立了3个1D DWT组成的流水化模型,设计中利用有限状态机(FSM)控制流程.仿真实验证明,设计方法正确有效,处理速度比串行方式提高约66%,工作频率达59 MHz,可满足视频编码器的实时性要求.By studying three dimensional discrete wavelet transform （3D DWT） core algorithm in deepness： the paper divides it into three one dimensional discrete wavelet transforms （1D DWT）. Based on the implementation of 3D DWT software, a VLSI architecture of paralell design is produced. It needs three double port RAM to store the temporay results and transpose the matrix, then builds up a pipelining model composed of three 1D DWT. In this design the finite state machine（FSM） is well used to control the flow. Compared with the serial mode, the experimental results of post synthesized simulation show that the method of design is correct and effective. It can increase processing speed about 66 %, and work with 59 MHz, meeting the real time needs of video encoder.

关 键 词：三维离散小波变换 并行化设计 矩阵转置 有限状态机 

分 类 号：TN492[电子电信—微电子学与固体电子学]