Nyquist电流型7位20MHz采样率CMOS数模转换器  

A 7-bit 20 MSample/s Nyquist Current-steering CMOS DAC

作　　者：邵滨[1] 李丹[1] 王方林[1] 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《固体电子学研究与进展》2006年第1期111-115,127,共6页Research & Progress of SSE

摘　　要：介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。This paper describes the design and the test results of a 7-bit high-speed CMOS DAC, which is implemented using a segmented architecture with 5 MSBs in unary way and 2 LSBs in binary way. Current-source matching, glitch reduction, and error compensation aspects are considered. This DAC is fabricated by 0. 35 μm Chartered double-poly four-metal CMOS technology. Experimental results show that a conversion rate of 20 MHz is achievable with differential and integral linearity errors of ±0. 2 LSB and ±0. 35 LSB, respectively. The full scale set- up time is 20 ns and the chip area is 0.17 mm×0. 23 mm. The power consumption is 3 mW for a single 3.3 V power supply.

关 键 词：电流源匹配 陷阱毛刺 误差补偿 

分 类 号：TN042[电子电信—物理电子学] TN492