基于FPGA的高速Viterbi译码器优化设计和实现  

Optimal Design and Realization of the High Speed Viterbi Code Converter Based on FPGA

作　　者：傅民仓[1] 冯立杰[1] 李文波[1] 

机构地区：[1]武警工程学院,陕西西安710086

出　　处：《现代电子技术》2006年第7期52-54,共3页Modern Electronics Technique

摘　　要：卷积码作为信道纠错编码在通信中得到了广泛的应用,而其相应的Viterbi译码器随着约束度N的增大其硬件复杂度成指数增加,硬件复杂度的大小决定译码速度。采用预计算的思想,避免了常规算法中的重复计算;对Viterbi译码器的核心模块ACS进行了优化设计,提出了一种FPGA实现方案,简化了接口电路、提高了速度。As the channel error correcting code, the convolution code has been extensive used in the communication. However, the hardware complexity of the corresponding Viterbi code converter increases in positive exponent along with the increase of the restrained degree N,while the hardware complexity decides the rate of the decoded operation. According to the thoughts of the predicted calculation which can avoid the repeated calculation in the conventional algorithm, the core module of the Viterbi code converter, ACS is optimized in the article. Moreover,a realized program based on FPGA is put forward,by which the interface circuit is simplified and the rate is increased.

关 键 词：卷积码 VITERBI译码 ACS预计算 FPGA 

分 类 号：TN764[电子电信—电路与系统]