MPEG-4视频编码器纹理填充模块的VLSI结构设计  

VLSI architecture design of texture padding for MPEG-4 encoder

作　　者：洪泽宏[1] 王占辉[1] 

机构地区：[1]海军工程大学电气与信息工程学院,湖北武汉430033

出　　处：《海军工程大学学报》2006年第2期77-82,共6页Journal of Naval University of Engineering

摘　　要：研究了MPEG-4纹理填充算法的特点,设计了纹理填充硬件实现的VLSI结构.在Xilinx ISE6.1i集成开发环境下,采用VHDL对该结构进行了描述,并使用了电子设计自动化(EDA)工具进行了模拟和验证.仿真和综合结果表明,所设计的VLSI处理器,逻辑功能完全正确,而且可以满足MPEG-4 Core Profiles&Level2的实时编码要求,可用于MPEG-4的VLSI实现.One important new feature in MPEG-4 is the texture padding technique. The VLSI architecture is designed according to the characteristics of the texture padding. The VLSI architecture and implementation in terms of VHDL are designed in the Xilinx ISE6. li environment, and some simulations are made by using EDA devices. The experimental results show that the VLSI processor designed can correctly perform logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.

关 键 词：超大规模集成电路 MPEG-4 纹理填充 

分 类 号：TM154.2[电气工程—电工理论与新技术] TN76[电子电信—电路与系统]