基于Montgomery模乘的RSA算法VLSI实现  

VLSI implementation for RSA algorithm based on Montgomery modular multiplication

作　　者：江隽文[1] 周玉洁[1] 

机构地区：[1]上海交通大学信息安全学院,上海200030

出　　处：《信息技术》2006年第4期85-88,161,共5页Information Technology

摘　　要：介绍了一种基于可伸展的Montgomery模乘结构的1024位RSA加解密芯片实现。设计采用的新型心动阵列结构,可以在有效控制芯片面积的前提下,极大地提高运算频率,从而提高运算速度。经过ModelSim仿真和Design Compiler综合,与当前已发表的RSA芯片设计相比,该设计在面积和速度上均有优势。In this paper a 1024 - bits RSA encryption chip based on sc.l.hle montgomery modular multiplier is proposed. It adopts a new systolic array architecture, which can improve the speed by increasing the frequency without the size increased. This design has been simulated by ModelSim and synthesized by Design Compiler. Compared with other RSA IC designs, the design has the advantage of small size and high speed.

关 键 词：RSA MONTGOMERY 模乘 心动阵列 模幂 

分 类 号：TN918.4[电子电信—通信与信息系统]