一种面向SOC的衬底噪声宏模型  

SOC Oriented Substrate Noise Macromodel

作　　者：吴晓鹏[1] 杨银堂[1] 朱樟明[1] 

机构地区：[1]西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《半导体技术》2006年第5期353-356,360,共5页Semiconductor Technology

摘　　要：针对SOC中常见的衬底噪声耦合问题,通过将器件模拟与拟合法相结合,基于0.25μm CMOS工艺提取衬底结构参数建立了电阻宏模型。该模型被应用于CMOS放大器电路,利用Hspice进行仿真,仿真结果表明,该模型从时、频域角度都能较好地表征出衬底噪声对模拟电路性能的影响,对深亚微米混合信号电路设计具有重要的指导意义。Using the device simulation and nonlinear curve fitting technology, a resistance macromodel of heavily doped epi-substrate made in deep-submicrometer technology was extracted, which is based on the 0.25μ m CMOS process. The macromodel was applied to a CMOS amplifier. And then the simulation was performed with Hspice in both the time domain and frequency domain. The results fit well with the device simulation and characterize the substrate noise coupling, it is of an important instructional significance for DSM mixed-signal circuit design.

关 键 词：衬底噪声 系统集成芯片 宏模型 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN43