深亚微米CMOS混合信号电路衬底噪声耦合宏模型  

The Substrate Noise Coupling Resistance Macromodel for Deep-submicron CMOS Mixed-Signal ICs

作　　者：吴晓鹏[1] 杨银堂[1] 朱樟明[1] 

机构地区：[1]西安电子科技大学微电子所,陕西西安710071

出　　处：《微电子学与计算机》2006年第5期128-131,135,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(60476046);国家863计划项目(2002AA1Z1210);电子元器件可靠性重点实验室基金项目(51433030304DZ01)

摘　　要：提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型。该宏模型通过器件模拟与非线性拟合相结合的方法建立,使衬底寄生参数的提取更加方便,同时保障了深亚微米电路特性的模拟精度。此外,该宏模型结构简单,可以得到与器件模拟基本一致的模拟结果,并可以方便地嵌入SPICE中进行一定规模的电路模拟。A resistance macromodel for deep-submicron process epi-type substrate based on the 2D device simulation is presented. The macromodel is built up with the combination of device simulation and nonlinear curve fit, which makes the extraction of the substrate parasitic parameters more convenient and the circuit simulation more accurate. Furthermore, its circuit structure is simple and it can be implemented easily in SPICE program for circuit simulations.

关 键 词：衬底噪声 数模混合电路 电阻宏模型 CMOS 

分 类 号：TN43[电子电信—微电子学与固体电子学]