一种I^2C总线接口的串行时钟芯片  

A serial clock chip with I^2C bus interfaces

作　　者：应建华[1] 陈艳[1] 郭艳[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2006年第5期62-64,共3页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：湖北省信息产业专项资金资助项目(05060)

摘　　要：论述了一种采用I2C总线接口的串行实时时钟芯片的设计方法.该芯片是一个低功耗、完全BCD码的时钟/日历芯片,地址和数据通过I2C双向数据总线串行传输.时钟/日历提供秒、分、时、日、星期、月和年的时间信息;集成的249 byte的静态随机存储器(SRAM)可用于存储临时信息;内置了电源电压监控电路,可使芯片在掉电时自动转入电池供电模式,并对SRAM进行掉电保护;与微处理器连接时,只占用CPU的2条I/O口线(SDA口线和SCL口线),数据传输速率最高可达400 kHz.Described was a design of a serial real-time clock chip with VC bus interfaces, which was a low power, full binary-coded decimal （BCD） clock/calendar chip, and whose address and data were transferred serially through an I^2C bidirectional bus. The clock/calendar could provide the time information such as second, minute, hour, day, date, month and year and so on. In the chip, an embedded 249 byte nonvolatile SRAM could be used to store temporary information; a built-in power sense circuit could detect power failures and automatically switch to the battery backup mode with information keeping in the SRAM. This chip occupies only two I/O wires （SDA and SCL） when it is connected to microprocessors and can operate under 400 kHz clock rate condition.

关 键 词：I^2C总线 实时时钟 串行接口 静态随机存储器 

分 类 号：TN46[电子电信—微电子学与固体电子学]