伪随机计数器的设计原理  

A Design Theory of Pseudo Random Counter[KH*2D]

作　　者：郑艳梅[1] 方葛丰[1] 张丹[1] 

机构地区：[1]电子测试技术国家重点实验室

出　　处：《电子测量与仪器学报》2006年第2期89-92,共4页Journal of Electronic Measurement and Instrumentation

摘　　要：传统线性加减计数器的进位结构制约了计数器硬件在高速度下的应用,将通讯系统中的伪随机序列的原理应用在计数中便可达到高速计数的目的。本文通过详细介绍4位伪随机计数器来说明伪随机计数器的原理。进而寻求实现任意位伪随机计数器的公式,即本原多项式。最后介绍了一些经过FPGA仿真的实验数据,数据对比了加减计数器和伪随机计数器在运算速度上的显著差距。The carry structure of the traditional linear Plus-Minus Counter restricts its application in high-speed field. Applying the theory of pseudo random sequence to counter will make high-speed counting come true. This paper simply introduced the theory of Plus-Minus Counter, and expanded the design theory of Pseudo Random Counter by actualizing a 4-bit PRC. It tried to find the formula of arbitrary bit PRC, namely Essential Polynomial. Because of the Complexity of the Essential Polynomial＇s deduction, this paper introduced the technique to actualize high bit PRC combining two or more low bit Pseudo Random Counters, and recommended the reasonable combining way that was applied by the author and coorkers. Finally, this paper provided some test data by FPGA simulation. The test data showed the obvious difference of the operating speed between Plus-Minus Counter and Pseudo Random Counter. If considering the aspect of actual hardware spending, Pseudo Random Counter will be more advantageous.

关 键 词：伪随机序列 线性反馈移位寄存器 本原多项式 伪随机计数器 加减计数器 现场可编程门阵列 

分 类 号：TN914.42[电子电信—通信与信息系统] TP332.12[电子电信—信息与通信工程]