并行浮点加法器架构与核心算法的研究  

Research on Parallel Architecture and Core Arithmetic of Floating-point Adder

作　　者：陈弦[1] 张伟功[1] 于伦正[1] 

机构地区：[1]西安微电子技术研究所,西安710054

出　　处：《计算机工程与应用》2006年第17期53-55,75,共4页Computer Engineering and Applications

摘　　要：考虑到浮点运算在图形处理中的重要作用,依据速度和面积的优化原理,文章从两个方面对FAU结构中最复杂的双精度浮点加法进行了研究。其一:在结构上采用了三条相互并行的主线,设计了一种尽可能并行处理的三级浮点流水结构,极大地提高了运算的速度,节约了芯片资源;其二:对结构中制约浮点加法速度的关键运算——尾加和移位操作进行了创新设计与实现,并就设计的先进性和高速性与传统设计进行了参数比较和综合分析。The speed of graphics process is decided by floating-point arithmetic;in the article,the most complex arithmetic in floating-point arithmetic unit,double-precision floating-point adder is researched in two sides based on speed and area optimization theory.For one thing,three pipeline parallel architecture of floating-point adder is designed by three nearly separating parallel main lines.This parallel architecture boosts the speed and saves the chip resource. For another thing,this paper focuses on the critical arithmetic,fraction adder and shifter which restricts the speed of floating-point adder.An innovative design and implementation of parallel fractions adder as well as fast fraction shifter are discussed in detail in this paper.ln additional,the advantages and high speed of these designs are verified by comparison with traditional way and comprehensive analysis.

关 键 词：核心算法 浮点加法器 并行 FAU 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]