基于VHDL的全数字分数分频器设计  

The Design of Total Digitized Fractional Frequency Divider Based on VHDL

作　　者：尹辉炳[1] 张涛[1] 

机构地区：[1]中国科学院上海技术物理研究所,上海200083

出　　处：《科学技术与工程》2006年第12期1609-1611,1616,共4页Science Technology and Engineering

摘　　要：介绍了全数字化的分数分频器的两种设计方法,分析了它们的特点,然后采用VHDL硬件描述语言设计了全数字化的分数分频器,并且给出了设计任意分数分频器的方法。Two methods of designing total digitized frequency divider are introduced and their characteristics are analyzed. Then the total digitized factional frequency divider using VHDL hardware description language is implemented and the method of designing arbitrary fractional frequency divider is supplied.

关 键 词：VHDL FPGA/CPLD分数分频器 

分 类 号：TN742.1[电子电信—电路与系统]