高性能除法电路仿真与实现  

Simulating and Implementation of High Performance Division

作　　者：刘慧英[1] 戴春蕾[1] 高茁[2] 

机构地区：[1]西北工业大学自动化学院,陕西西安710072 [2]中国科学院计算技术研究所,北京100080

出　　处：《仪表技术与传感器》2006年第6期38-39,60,共3页Instrument Technique and Sensor

摘　　要：比较了当今主流处理器中除法器的几种算法,通过分析,得知SRT运算的硬件结构简单、面积小、功耗小。对SRT算法进行了改进,使用了两级重叠基-2使其变化为基-4的方法,速度较普通的基-2算法提高了1倍,而硬件代价却远小于基-4的方法。用verilog语言对其进行了描述,modelsim进行了功能仿真验证,synplicity进行综合。结果表明该电路具有较好的速度、面积和功耗的折衷。该除法器可以广泛地应用到各种嵌入式和通用处理器中,有很高的实用价值。Compared several algorithm of division of mainstream computer. Analyzed these three algorithms and find that SRT algorithm has the virtue of simple hardware structure, less area and low power. Modifid and realized the SRT algorithm, used overlap radix- 2 to realize the radix - 4, which made the speed double. The circuit was described using verilog language, verified using modelsim and synthesized with synplicity. The result show the circuit has higher speed, area and power tradeoff. This division circuit can be used in embedded or general purpose processor.

关 键 词：除法 基 商选择函数 仿真 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]