一种64位浮点乘加器的设计与实现  

Design and Implementation of a 64-bit Floating-point Multiply-Add Fused Unit

作　　者：靳战鹏[1] 白永强[1] 沈绪榜[1] 

机构地区：[1]西北工业大学计算机学院,西安710072

出　　处：《计算机工程与应用》2006年第18期95-98,共4页Computer Engineering and Applications

基　　金：西北工业大学"研究生创业种子基金"资助项目(编号:Z20040050)

摘　　要：乘加操作是许多科学与工程应用中的基本操作,特别是在图形加速器和DSP等应用领域,浮点乘加器有着广泛的应用。论文针对PowerPC603e微处理器系统,基于SMIC0.25μm1P5MCMOS工艺,采用正向全定制的电路及版图设计方法,设计实现了一个综合使用改进Booth算法、平衡的4-2压缩器构成的Wallace树形结构、先行进位加法器的支持IEEE-754标准的64bit浮点乘加器。The multiply-add operation is fundamental in many scientific and engineering applications,especially in the field of image processing and DSP,the floating-point multiply-adder has been widely used.Aiming at PowerPC603e microprocessor system,a 64-bit multiply-add fused floating-point unit which supports IEEE-754 double precision floating-point standard is implemented in SMIC 0.25um 1P5M CMOS technology with the method of positive direction full-custom circuit ＆ layout design.It uses a comprehensive method including improved Booth algorithm,Wallace com- pressing tree-unit balanced 4-2 compress composing of balanced 4-2 compressing units and carry-save adders etc.

关 键 词：改进Booth2算法 浮点乘加器 WALLACE树 全定制 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]