基于Verilog HDL双向端口的设计与实现  

Design and Implementation of Dual-port Based on Verilog HDL

作　　者：李雪梅[1] 路而红[1] 

机构地区：[1]北京电子科技学院,北京100070

出　　处：《现代电子技术》2006年第14期73-75,共3页Modern Electronics Technique

基　　金：学院信息安全重点实验室基金项目

摘　　要：在数字系统的FPGA设计中经常用到双向端口,即同时具有输入/输出功能的端口,而Verilog HDL描述的双向端口在某些情况下不能被直接赋值使用。介绍了基于Verilog HDL双向端口的三种实现方法:使用“assign”语句、元件例化(module instantiate)、图形与文本混合设计,说明了设计过程,并给出了相关程序及仿真波形。仿真结果与测试结果一致,说明该实现双向端口的方法可行。The dual-port which has Input/Output function is usually used in digital FPGA design. While the dual-port described with Verilog HDL can not be evaluated directly in some instance. This paper introduces three methods for imple-menting dual-port based on Verilog HDL：＂assign＂sentence, module instantiate and mixing design with graph and ,text. Besides explanation of design,this paper gives programs and simulation waves. The results of simulation are consistent with the results got from the experiment. So the methods in this paper are proved to be feasible.

关 键 词：VERILOG HDL 双向端口 仿真 

分 类 号：TN334.4[电子电信—物理电子学]