基于SpartanⅡXC2S100的I^2 C总线通信  

Design of I^2 C-Bus Interface Based on SpartanⅡXC2S100

作　　者：胡文静[1] 李外云[1] 刘锦高[1] 

机构地区：[1]华东师范大学信息科学与技术学院

出　　处：《华东师范大学学报（自然科学版）》2006年第4期11-15,共5页Journal of East China Normal University(Natural Science)

基　　金：上海市科委AM基金(D206)

摘　　要：介绍了I^2C总线协议及基于FPGA芯片的I^2C总线接口结构框图．提出了复杂时序电路状态机嵌套的设计思想,并给出了基于Verilog HDL的I^2C总线接口电路的硬件描述．在ISE 6．1i平台下结合ModelSim SE 5．7进行了设计仿真,实现了XC2S100对I^2C总线器件的读写操作．The protocol and principle of I^2C Bus were introduced. The framework of I^2C-Bus based on FPGA was proposed. The idea of nesting state-machine of complicated timing-circuit and the hardware description of I^2C-Bus interface by Verilog HDL were presented. The simulation of designing under the Xilinx ISE 6.1 i development platform combined with ModelSim SE 5.7 was made and the operation on I^2C device based on Spartan Ⅱ XC2S100 was implemented.

关 键 词：现场可编程门阵列(FPGA) XC2S100 I^2C总线 VERILOG HDL 状态机嵌套 

分 类 号：TN915.04[电子电信—通信与信息系统]