一种线长和时延双重驱动的布局算法  

A new placement algorithm based on wielength minimization and timing-driven optimization objective

作　　者：王东平[1] 毛军发[1] 

机构地区：[1]上海交通大学电子工程系

出　　处：《微计算机信息》2006年第08S期307-309,共3页Control & Automation

基　　金：国家自然科学基金委创新研究群体基金(90207010);华为科技基金

摘　　要：针对标准单元模式的超大规模集成电路布局问题,本文提了一种新的基于线长和时延双重优化目标的布局算法。在以优化线长为目标函数的布局结果基础上,进一步优化了芯片的时延特性,并通过算法设计较好地解决了二者优化方向的一致性。通过标准单元测试电路的实验结果比对,该算法在线长及时延优化方面综合性能良好。Facing the severe challenges of placement in very large scale integrated circuits based on standard cell, a new placement algorithm based on both timing-driven and power minimization optimization objective was presented. Based on the placement result which was optimized by wirelength minimization objective, the delay of the circuit was minimized, besides, this optimization method was well adopted to combine the timing-driven optimization and wirelength minimization. According to the experimental results of MCNC （microelectronics centre of north -Carolina） standard cell benchmarks, the total wielength and longest path delay were both improved.

关 键 词：互连线 布局 线长 时延 

分 类 号：TN402[电子电信—微电子学与固体电子学]