嵌入式协调设计中的系统级验证方法及应用  

System-level co-verification and its application

作　　者：范彧[1] 王世好[2] 

机构地区：[1]中央民族大学数学与计算机学院,北京100081 [2]北京计算机技术及应用研究所,北京100854

出　　处：《计算机工程与设计》2006年第14期2698-2701,共4页Computer Engineering and Design

摘　　要：协同验证是在嵌入式系统协调设计过程中用以检验系统功能是否正确的有效手段。由于精确指令集模拟器模拟的细节多、速度慢,通常成为复杂嵌入式系统协同验证的瓶颈,因此提出使用RTOS软件模拟器和指令集模拟器相结合的多层次验证方法,提高了复杂嵌入式系统的验证速度,并通过某图像压缩系统的验证实例,说明该验证方法的有效性。Simulator is an effective means of co-design and co-verification in embedded hardware/software mixed system. Instruction set simulator （ISS） is a popular verifying tool, which accepts inquest from outside, outputs simulating result, drives peripheral equipment, just like target processor. However, the simulation speed of ISS is so slow that it can not applied in the design of complicated systems. In order to simplify the processes of co-verification and improve the performance of simulation, a new co-verifying strategy is developed, which is based on interface pre-verification and a multi-level system structure. At last, the method is applied in an image compression application. The result demonstrates the validity of this method.

关 键 词：嵌入式系统 协同模拟 模拟器 实时操作系统 指令集模拟器 系统级验证 

分 类 号：TP15[自动化与计算机技术—控制理论与控制工程]