基于VelociTI体系结构的DSP指令分配的实现  

Realization of Instruction Dispatch for DSP Based on VelociTI Architecture

作　　者：胡正伟[1] 韩月秋 陈禾[1] 张晓明[1] 

机构地区：[1]北京理工大学电子工程系

出　　处：《计算机工程与应用》2006年第21期71-73,共3页Computer Engineering and Applications

基　　金：国家部委预研项目

摘　　要：在设计基于VelociTI体系结构的数字信号处理器过程中,为了高速实现并行指令的分配,提出了一种基于该体系结构的指令分配方法:排序法。该方法结合决策树原理实现取指包指令并行性测试,并将处理器的功能单元按照一个规定的顺序排列,使每一个功能单元与执行包的某一个字段对应,将执行包中的指令根据译码的结果和功能单元的顺序进行重新排序,从而完成指令到功能单元的分配。仿真结果证明该方法是十分有效的。A new design method of instruction dispatch for digital signal processor which is based on VelociTI architecture has been presented in this paper.We call this method as ordered method.This method tests the parallelism by decision tree principle and arranges all function units into a firmed order so that each function unit can match with some part of one execute packet.According to the result of decode and the order of function units,instructions are reordered in each execute packet.Then the target of instruction dispatch is realized.The simulation result can confirm the quality of this method.

关 键 词：VelociTI 指令分配 排序 决策树 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]