中长帧非规则LDPC码译码器的FPGA实现  

FPGA Implementation of Irregular LDPC Code Decoder

作　　者：范雷[1] 王琳[1] 肖旻[1] 

机构地区：[1]厦门大学电子工程系,福建省厦门市361005

出　　处：《电子工程师》2006年第8期21-24,共4页Electronic Engineer

摘　　要：LDPC(低密度奇偶校验码)是一种优秀的线性分组码,是目前距香农限最近的一类纠错编码。与Turbo码相比,LDPC码能得到更高的译码速度和更好的误码率性能,从而被认为是下一代通信系统和磁盘存储系统中备选的纠错编码。简要介绍了适于硬件实现的LDPC码译码算法,并基于软判决译码规则,使用Verilog硬件描述语言,在X ilinx V irtex2 6000 FPGA上实现了码率为1/2、帧长504bit的非规则LDPC码译码器。Low Density Parity Check （LDPC） code is a good linear block code, which performs at a rate extremely close to the Shannon limit capacity. Compared with Turbo code, LDPC code performs faster decoding speed and better BER performance and is considered to be one of suitable codes for 4G communication system and storage system. This paper introduces a decode algorithm which is suitable for hardware implementation and a fully parallel decoder based on a frame of 504 bits for irregular LDPC codes is implemented on Xilinx FPGA XC2V6000 device with Verilog language.

关 键 词：LDPC码 非规则码 FPGA实现 

分 类 号：TN911.1[电子电信—通信与信息系统]