基于MIPS内核的SoC软硬件协同仿真  

Software and Hardware Co-simulation of SoC Based on MIPS Core

作　　者：王江[1] 刘佩林[1] 陈颖琪[1] 

机构地区：[1]上海交通大学图像通信与信息处理研究所,上海200030

出　　处：《计算机工程》2006年第16期247-249,共3页Computer Engineering

基　　金：国家"863"计划基金资助项目(2003AA1Z1070)

摘　　要：针对基于MIPS系列处理器内核的高清电视解码SoC,构建了一个软硬件协同仿真环境。连接MIPS处理器内核的VMC模型和SoC的RTL模型,利用VMC模型支持MIPS指令集的特性运行测试汇编程序,实现了SoC软硬件的同步调试,有效地提高了系统验证的效率。A software and hardware co-simulation environment has been built for the HDTV decoder SoC based on MIPS processor core. Using the VMC＇s support of MIPS instruction set, and by running the assemble program for test in this environment which connects the VMC model of the MIPS processor core and the RTL model of the HDTV SoC, the software and hardware of SoC synchronously can be debuged, which can lead to a high-efficiency of SoC verification.

关 键 词：VMC 片上系统 软硬件协同仿真 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]